/*
CPU				AXI4
AXI_CDC			AXI4
AXI_Crossbar	AXI4
UART0			AXI3/AXI4
CONFRG			AXI3/AXI4
*/

`include "config.h"
`include "iopad.svh"	//for ASIC io pad

module soc_top #(parameter SIMULATION=1'b0)
(
    input           clk,                //50MHz 时钟输入
    input           reset,              //BTN6手动复位按钮，带消抖电路，按下时为1
	//confreg
    input  [3:0]    touch_btn,          //BTN1~BTN4，按钮开关，按下时为1
    input  [31:0]   dip_sw,             //32位拨码开关，拨到“ON”时1
    output [15:0]   leds,               //16位LED，输出时1点亮
    output [7:0]    dpy0,               //数码管低位信号，包括小数点，输出1点亮 
    output [7:0]    dpy1,               //数码管高位信号，包括小数点，输出1点亮
    //BaseRAM信号
    inout  [31:0]   base_ram_data,      //BaseRAM数据
    output [19:0]   base_ram_addr,      //BaseRAM地址
    output [ 3:0]   base_ram_be_n,      //BaseRAM字节使能，低有效
    output          base_ram_ce_n,      //BaseRAM片
    output          base_ram_oe_n,      //BaseRAM读使能
    output          base_ram_we_n,      //BaseRAM写使能
    //ExtRAM信号
    inout  [31:0]   ext_ram_data,       //ExtRAM数据
    output [19:0]   ext_ram_addr,       //ExtRAM地址
    output [ 3:0]   ext_ram_be_n,       //ExtRAM字节使能
    output          ext_ram_ce_n,       //ExtRAM片
    output          ext_ram_oe_n,       //ExtRAM读使能
    output          ext_ram_we_n,       //ExtRAM写使能
    //------uart-------
    inout           UART_RX,            //串口RX
    inout           UART_TX,            //串口TX
	//clock output
	output          clk_o              	//XTALO for ASIC
);

	//IO pad ---------------------------------------------
	//ASIC io pad
	PX3W PAD_CLK_IN (.XIN(clk), .XOUT(clk_o), .XC(clk_i));  
	`IPADU_GEN_SIMPLE(reset)  
	`IPAD_GEN_VEC_SIMPLE(touch_btn)  
	`IPAD_GEN_VEC_SIMPLE(dip_sw)  
	`OPAD_GEN_VEC_SIMPLE(leds)  
	`OPAD_GEN_VEC_SIMPLE(dpy0)  
	`OPAD_GEN_VEC_SIMPLE(dpy1)  
	`IOPAD_GEN_VEC_SIMPLE(base_ram_data)  
	`OPAD_GEN_VEC_SIMPLE(base_ram_addr)  
	`OPAD_GEN_VEC_SIMPLE(base_ram_be_n)  
	`OPAD_GEN_SIMPLE(base_ram_ce_n)  
	`OPAD_GEN_SIMPLE(base_ram_oe_n)  
	`OPAD_GEN_SIMPLE(base_ram_we_n)  
	`IOPAD_GEN_VEC_SIMPLE(ext_ram_data)  
	`OPAD_GEN_VEC_SIMPLE(ext_ram_addr)  
	`OPAD_GEN_VEC_SIMPLE(ext_ram_be_n)  
	`OPAD_GEN_SIMPLE(ext_ram_ce_n)  
	`OPAD_GEN_SIMPLE(ext_ram_oe_n)  
	`OPAD_GEN_SIMPLE(ext_ram_we_n)  
	`IOPAD_GEN_SIMPLE(UART_RX)  
	`IOPAD_GEN_SIMPLE(UART_TX)  
	//IO pad ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


	//CLK GEN ---------------------------------------------
	//for chip io
	wire cpu_clk;
	wire cpu_resetn;
	wire sys_clk;
	wire sys_resetn;
	wire sm2_clk;
	wire sm2_resetn;
	
	`ifdef USE_FPGA
		//for FPGA
		generate if(SIMULATION) begin: sim_clk
			//simulation clk.
			reg clk_sim;
			reg sm2_clk_sim;
			initial begin
				clk_sim = 1'b0;
				sm2_clk_sim = 1'b0;
			end
			always #15 clk_sim = ~clk_sim;
			always #25 sm2_clk_sim = ~sm2_clk_sim;

			assign cpu_clk = clk_sim;
			assign sys_clk = clk_i;
			assign sm2_clk = sm2_clk_sim;
			rst_sync u_rst_sys(
				.clk(sys_clk),
				.rst_n_in(~reset_i),
				.rst_n_out(sys_resetn)
			);
			rst_sync u_rst_cpu(
				.clk(cpu_clk),
				.rst_n_in(sys_resetn),
				.rst_n_out(cpu_resetn)
			);
			rst_sync u_rst_sm2(
				.clk(cpu_clk),
				.rst_n_in(sys_resetn),
				.rst_n_out(sm2_resetn)
			);
		end
		else begin: pll_clk
			clk_pll u_clk_pll(
				.cpu_clk    (cpu_clk),
				.sys_clk    (sys_clk),
				.sm2_clk    (sm2_clk),
				.resetn     (~reset_i),
				.locked     (pll_locked),
				.clk_in1    (clk_i)
			);
			rst_sync u_rst_sys(
				.clk(sys_clk),
				.rst_n_in(pll_locked),
				.rst_n_out(sys_resetn)
			);
			rst_sync u_rst_cpu(
				.clk(cpu_clk),
				.rst_n_in(sys_resetn),
				.rst_n_out(cpu_resetn)
			);
			rst_sync u_rst_sm2(
				.clk(cpu_clk),
				.rst_n_in(sys_resetn),
				.rst_n_out(sm2_resetn)
			);
		end
		endgenerate
	`else
		//for ASIC
		assign cpu_clk = clk_i;  
		assign sys_clk = clk_i;
		assign sm2_clk = clk_i;
		rst_sync u_rst_sys(  
				.clk(sys_clk),
				.rst_n_in(~reset_i),  
				.rst_n_out(sys_resetn)  
			);  
			rst_sync u_rst_cpu(  
				.clk(cpu_clk),  
				.rst_n_in(sys_resetn),  
				.rst_n_out(cpu_resetn)  
			);
			rst_sync u_rst_sm2(
				.clk(cpu_clk),
				.rst_n_in(sys_resetn),
				.rst_n_out(sm2_resetn)
			);
	`endif
	//CLK GEN ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


	//AXI CONFREG  ---------------------------------------------
	wire [4:0]  confreg_awid;
	wire [31:0] confreg_awaddr;
	wire [7:0]  confreg_awlen;
	wire [2:0]  confreg_awsize;
	wire [1:0]  confreg_awburst;
	wire [1:0]  confreg_awlock;
	wire [3:0]  confreg_awcache;
	wire [2:0]  confreg_awprot;
	wire        confreg_awvalid; 
	wire        confreg_awready;
	wire        confreg_wvalid;
	wire [31:0] confreg_wdata;
	wire [3:0]  confreg_wstrb;
	wire        confreg_wlast;
	wire        confreg_wready;
	wire        confreg_bready;
	wire        confreg_bvalid;
	wire [4:0]  confreg_bid;
	wire [1:0]  confreg_bresp;
	wire        confreg_arvalid;
	wire        confreg_arready;
	wire [31:0] confreg_araddr;
	wire [4:0]  confreg_arid;
	wire [7:0]  confreg_arlen;
	wire [2:0]  confreg_arsize;
	wire [1:0]  confreg_arburst;
	wire [1:0]  confreg_arlock;
	wire [3:0]  confreg_arcache;
	wire [2:0]  confreg_arprot;
	wire        confreg_rvalid;
	wire        confreg_rready;
	wire [31:0] confreg_rdata;
	wire [4:0]  confreg_rid;
	wire [1:0]  confreg_rresp;
	wire        confreg_rlast;
	wire        confreg_int;
	wire [26:0]	confreg_exti;
	`ifdef USE_CRYPTO
		assign confreg_exti = {24'b0, sm2_done_int, sm3_done_int, sm4_done_int};
	`else
		assign confreg_exti = 27'b0;
	`endif
	//AXI CONFREG ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


	//CPU wire ---------------------------------------------
	wire [3:0]  cpu_arid;
	wire [31:0] cpu_araddr;
	wire [7:0]  cpu_arlen;
	wire [2:0]  cpu_arsize;
	wire [1:0]  cpu_arburst;
	wire [1:0]  cpu_arlock;
	wire [3:0]  cpu_arcache;
	wire [2:0]  cpu_arprot;
	wire        cpu_arvalid;
	wire        cpu_arready;
	wire [3:0]  cpu_rid;
	wire [31:0] cpu_rdata;
	wire [1:0]  cpu_rresp;
	wire        cpu_rlast;
	wire        cpu_rvalid;
	wire        cpu_rready;
	wire [3:0]  cpu_awid;
	wire [31:0] cpu_awaddr;
	wire [7:0]  cpu_awlen;
	wire [2:0]  cpu_awsize;
	wire [1:0]  cpu_awburst;
	wire [1:0]  cpu_awlock;
	wire [3:0]  cpu_awcache;
	wire [2:0]  cpu_awprot;
	wire        cpu_awvalid;
	wire        cpu_awready;
	wire [3:0]  cpu_wid;
	wire [31:0] cpu_wdata;
	wire [3:0]  cpu_wstrb;
	wire        cpu_wlast;
	wire        cpu_wvalid;
	wire        cpu_wready;
	wire [3:0]  cpu_bid;
	wire [1:0]  cpu_bresp;
	wire        cpu_bvalid;
	wire        cpu_bready;
	//debug
	wire [31:0] debug0_wb_pc;
	wire [31:0] debug0_wb_inst;
	wire [ 3:0] debug0_wb_rf_wen;
	wire [ 4:0] debug0_wb_rf_wnum;
	wire [31:0] debug0_wb_rf_wdata;
	//int
	wire [7:0] cpu_intrpt;
	assign cpu_intrpt[0] = confreg_int;
	//assign cpu_intrpt[0] = 1'b0;
	assign cpu_intrpt[7:1] = 7'b0;
	//CPU wire ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


	//AXI CDC  ---------------------------------------------
	wire        cpu_sync_awvalid;
	wire        cpu_sync_awready;
	wire [31:0] cpu_sync_awaddr;
	wire [3:0]  cpu_sync_awid;
	wire [7:0]  cpu_sync_awlen;
	wire [2:0]  cpu_sync_awsize;
	wire [1:0]  cpu_sync_awburst;
	wire [1:0]  cpu_sync_awlock;
	wire [3:0]  cpu_sync_awcache;
	wire [2:0]  cpu_sync_awprot;
	wire        cpu_sync_wvalid;
	wire        cpu_sync_wready;
	wire [31:0] cpu_sync_wdata;
	wire [3:0]  cpu_sync_wstrb;
	wire        cpu_sync_wlast;
	wire        cpu_sync_bready;
	wire        cpu_sync_bvalid;
	wire [3:0]  cpu_sync_bid;
	wire [1:0]  cpu_sync_bresp;
	wire        cpu_sync_arvalid;
	wire        cpu_sync_arready;
	wire [31:0] cpu_sync_araddr;
	wire [3:0]  cpu_sync_arid;
	wire [7:0]  cpu_sync_arlen;
	wire [2:0]  cpu_sync_arsize;
	wire [1:0]  cpu_sync_arburst;
	wire [1:0]  cpu_sync_arlock;
	wire [3:0]  cpu_sync_arcache;
	wire [2:0]  cpu_sync_arprot;
	wire        cpu_sync_rvalid;
	wire        cpu_sync_rready;
	wire [31:0] cpu_sync_rdata;
	wire [3:0]  cpu_sync_rid;
	wire [1:0]  cpu_sync_rresp;
	wire        cpu_sync_rlast;
	//AXI CDC ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


	//AXI SRAM  ---------------------------------------------
	wire        ram_awvalid;
	wire        ram_awready;
	wire [31:0] ram_awaddr;
	wire [4:0]  ram_awid;
	wire [7:0]  ram_awlen;
	wire [2:0]  ram_awsize;
	wire [1:0]  ram_awburst;
	wire [1:0]  ram_awlock;
	wire [3:0]  ram_awcache;
	wire [2:0]  ram_awprot;
	wire        ram_wvalid;
	wire        ram_wready;
	wire [31:0] ram_wdata;
	wire [3:0]  ram_wstrb;
	wire        ram_wlast;
	wire        ram_bready;
	wire        ram_bvalid;
	wire [4:0]  ram_bid;
	wire [1:0]  ram_bresp;
	wire        ram_arvalid;
	wire        ram_arready;
	wire [31:0] ram_araddr;
	wire [4:0]  ram_arid;
	wire [7:0]  ram_arlen;
	wire [2:0]  ram_arsize;
	wire [1:0]  ram_arburst;
	wire [1:0]  ram_arlock;
	wire [3:0]  ram_arcache;
	wire [2:0]  ram_arprot;
	wire        ram_rvalid;
	wire        ram_rready;
	wire [31:0] ram_rdata;
	wire [4:0]  ram_rid;
	wire [1:0]  ram_rresp;
	wire        ram_rlast;
	//AXI RAM wire ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


	//AXI UART  ---------------------------------------------
	//for int sys
	wire        uart0_int;
	//for AXI
	wire [4:0]  uart_awid;
	wire [31:0] uart_awaddr;
	wire [7:0]  uart_awlen;
	wire [2:0]  uart_awsize;
	wire [1:0]  uart_awburst;
	wire [1:0]  uart_awlock;
	wire [3:0]  uart_awcache;
	wire [2:0]  uart_awprot;
	wire        uart_awvalid;
	wire        uart_awready;
	wire        uart_wvalid;
	wire        uart_wready;
	wire [31:0] uart_wdata;
	wire [3:0]  uart_wstrb;
	wire        uart_wlast;
	wire        uart_bready;
	wire        uart_bvalid;
	wire [4:0]  uart_bid;
	wire [1:0]  uart_bresp;
	wire        uart_arvalid;
	wire        uart_arready;
	wire [31:0] uart_araddr;
	wire [4:0]  uart_arid;
	wire [7:0]  uart_arlen;
	wire [2:0]  uart_arsize;
	wire [1:0]  uart_arburst;
	wire [1:0]  uart_arlock;
	wire [3:0]  uart_arcache;
	wire [2:0]  uart_arprot;
	wire        uart_rvalid;
	wire        uart_rready;
	wire [31:0] uart_rdata;
	wire [4:0]  uart_rid;
	wire [1:0]  uart_rresp;
	wire        uart_rlast;
	//assign
	wire uart0_rts_o;
	wire uart0_dtr_o;
	wire uart0_cts_i;
	wire uart0_dcd_i;
	wire uart0_dsr_i;
	wire uart0_ri_i;
	assign uart0_cts_i = 1'b0;
	assign uart0_dcd_i = 1'b0;
	assign uart0_dsr_i = 1'b0;
	assign uart0_ri_i  = 1'b0;
	//AXI UART  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


	//AXI SM  -------------------------------------------------
	`ifdef USE_CRYPTO
		wire [4:0]  sm_awid;
		wire [31:0] sm_awaddr;
		wire [7:0]  sm_awlen;
		wire [2:0]  sm_awsize;
		wire [1:0]  sm_awburst;
		wire [1:0]  sm_awlock;
		wire [3:0]  sm_awcache;
		wire [2:0]  sm_awprot;
		wire        sm_awvalid; 
		wire        sm_awready;
		wire        sm_wvalid;
		wire [31:0] sm_wdata;
		wire [3:0]  sm_wstrb;
		wire        sm_wlast;
		wire        sm_wready;
		wire        sm_bready;
		wire        sm_bvalid;
		wire [4:0]  sm_bid;
		wire [1:0]  sm_bresp;
		wire        sm_arvalid;
		wire        sm_arready;
		wire [31:0] sm_araddr;
		wire [4:0]  sm_arid;
		wire [7:0]  sm_arlen;
		wire [2:0]  sm_arsize;
		wire [1:0]  sm_arburst;
		wire [1:0]  sm_arlock;
		wire [3:0]  sm_arcache;
		wire [2:0]  sm_arprot;
		wire        sm_rvalid;
		wire        sm_rready;
		wire [31:0] sm_rdata;
		wire [4:0]  sm_rid;
		wire [1:0]  sm_rresp;
		wire        sm_rlast;
		wire 		sm2_done_int;
		wire 		sm3_done_int;
		wire 		sm4_done_int;
	`endif
	//AXI SM ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


	//CPU module ---------------------------------------------
    core_top u_cpu(
        .intrpt     (cpu_intrpt),		//8位中断信号
        .aclk       (cpu_clk),
        .aresetn    (cpu_resetn),
        //读地址通道
        .arid       (cpu_arid),
        .araddr     (cpu_araddr),
        .arlen      (cpu_arlen),
        .arsize     (cpu_arsize),
        .arburst    (cpu_arburst),
        .arlock     (cpu_arlock),
        .arcache    (cpu_arcache),
        .arprot     (cpu_arprot),
        .arvalid    (cpu_arvalid),
        .arready    (cpu_arready),
        //读数据通道
        .rid        (cpu_rid),
        .rdata      (cpu_rdata),
        .rresp      (cpu_rresp),
        .rlast      (cpu_rlast),
        .rvalid     (cpu_rvalid),
        .rready     (cpu_rready),
        //写地址通道
        .awid       (cpu_awid),
        .awaddr     (cpu_awaddr),
        .awlen      (cpu_awlen),
        .awsize     (cpu_awsize),
        .awburst    (cpu_awburst),
        .awlock     (cpu_awlock),
        .awcache    (cpu_awcache),
        .awprot     (cpu_awprot),
        .awvalid    (cpu_awvalid),
        .awready    (cpu_awready),
        //写数据通道
        .wid        (cpu_wid),
        .wdata      (cpu_wdata),
        .wstrb      (cpu_wstrb),
        .wlast      (cpu_wlast),
        .wvalid     (cpu_wvalid),
        .wready     (cpu_wready),
        //写响应通道
        .bid        (cpu_bid),
        .bresp      (cpu_bresp),
        .bvalid     (cpu_bvalid),
        .bready     (cpu_bready),
        //已弃用
        .break_point    (1'b0),
        .infor_flag     (1'b0),
        .reg_num        (5'b0),
        .ws_valid       (),
        .rf_rdata       (),
        //写回阶段提供的调试信号
        .debug0_wb_pc       (debug0_wb_pc),
        .debug0_wb_inst     (debug0_wb_inst),
        .debug0_wb_rf_wen   (debug0_wb_rf_wen),
        .debug0_wb_rf_wnum  (debug0_wb_rf_wnum),
        .debug0_wb_rf_wdata (debug0_wb_rf_wdata)
        );
	//CPU module ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
	
	
	//CDC module ---------------------------------------------
    Axi_CDC u_Axi_CDC(
		//clk & rst
        .axiInClk       (cpu_clk),
        .axiInRst       (cpu_resetn),
        .axiOutClk      (sys_clk),
        .axiOutRst      (sys_resetn),
        //axi
        .axiIn_awvalid  (cpu_awvalid),
        .axiIn_awready  (cpu_awready),
        .axiIn_awaddr   (cpu_awaddr),
        .axiIn_awid     (cpu_awid),
        .axiIn_awlen    (cpu_awlen),
        .axiIn_awsize   (cpu_awsize),
        .axiIn_awburst  (cpu_awburst),
        .axiIn_awlock   (cpu_awlock[0]),
        .axiIn_awcache  (cpu_awcache),
        .axiIn_awprot   (cpu_awprot),
        .axiIn_wvalid   (cpu_wvalid),
        .axiIn_wready   (cpu_wready),
        .axiIn_wdata    (cpu_wdata),
        .axiIn_wstrb    (cpu_wstrb),
        .axiIn_wlast    (cpu_wlast),
        .axiIn_bvalid   (cpu_bvalid),
        .axiIn_bready   (cpu_bready),
        .axiIn_bid      (cpu_bid),
        .axiIn_bresp    (cpu_bresp),
        .axiIn_arvalid  (cpu_arvalid),
        .axiIn_arready  (cpu_arready),
        .axiIn_araddr   (cpu_araddr),
        .axiIn_arid     (cpu_arid),
        .axiIn_arlen    (cpu_arlen),
        .axiIn_arsize   (cpu_arsize),
        .axiIn_arburst  (cpu_arburst),
        .axiIn_arlock   (cpu_arlock[0]),
        .axiIn_arcache  (cpu_arcache),
        .axiIn_arprot   (cpu_arprot),
        .axiIn_rvalid   (cpu_rvalid),
        .axiIn_rready   (cpu_rready),
        .axiIn_rdata    (cpu_rdata),
        .axiIn_rid      (cpu_rid),
        .axiIn_rresp    (cpu_rresp),
        .axiIn_rlast    (cpu_rlast),
        .axiOut_awvalid (cpu_sync_awvalid),
        .axiOut_awready (cpu_sync_awready),
        .axiOut_awaddr  (cpu_sync_awaddr),
        .axiOut_awid    (cpu_sync_awid),
        .axiOut_awlen   (cpu_sync_awlen),
        .axiOut_awsize  (cpu_sync_awsize),
        .axiOut_awburst (cpu_sync_awburst),
        .axiOut_awlock  (cpu_sync_awlock[0]),
        .axiOut_awcache (cpu_sync_awcache),
        .axiOut_awprot  (cpu_sync_awprot),
        .axiOut_wvalid  (cpu_sync_wvalid),
        .axiOut_wready  (cpu_sync_wready),
        .axiOut_wdata   (cpu_sync_wdata),
        .axiOut_wstrb   (cpu_sync_wstrb),
        .axiOut_wlast   (cpu_sync_wlast),
        .axiOut_bvalid  (cpu_sync_bvalid),
        .axiOut_bready  (cpu_sync_bready),
        .axiOut_bid     (cpu_sync_bid),
        .axiOut_bresp   (cpu_sync_bresp),
        .axiOut_arvalid (cpu_sync_arvalid),
        .axiOut_arready (cpu_sync_arready),
        .axiOut_araddr  (cpu_sync_araddr),
        .axiOut_arid    (cpu_sync_arid),
        .axiOut_arlen   (cpu_sync_arlen),
        .axiOut_arsize  (cpu_sync_arsize),
        .axiOut_arburst (cpu_sync_arburst),
        .axiOut_arlock  (cpu_sync_arlock[0]),
        .axiOut_arcache (cpu_sync_arcache),
        .axiOut_arprot  (cpu_sync_arprot),
        .axiOut_rvalid  (cpu_sync_rvalid),
        .axiOut_rready  (cpu_sync_rready),
        .axiOut_rdata   (cpu_sync_rdata),
        .axiOut_rid     (cpu_sync_rid),
        .axiOut_rresp   (cpu_sync_rresp),
        .axiOut_rlast   (cpu_sync_rlast)
        );
	//CDC module ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
	
	
	//AXI module ---------------------------------------------
    AxiCrossbar_1x4 u_AxiCrossbar_1x4(
        .clk            (sys_clk),
        .resetn         (sys_resetn),
        //master 0 - CPU
        .axiIn_awvalid  (cpu_sync_awvalid),
        .axiIn_awready  (cpu_sync_awready),
        .axiIn_awaddr   (cpu_sync_awaddr),
        .axiIn_awid     (cpu_sync_awid),
        .axiIn_awlen    (cpu_sync_awlen),
        .axiIn_awsize   (cpu_sync_awsize),
        .axiIn_awburst  (cpu_sync_awburst),
        .axiIn_awlock   (cpu_sync_awlock[0]),
        .axiIn_awcache  (cpu_sync_awcache),
        .axiIn_awprot   (cpu_sync_awprot),
        .axiIn_wvalid   (cpu_sync_wvalid),
        .axiIn_wready   (cpu_sync_wready),
        .axiIn_wdata    (cpu_sync_wdata),
        .axiIn_wstrb    (cpu_sync_wstrb),
        .axiIn_wlast    (cpu_sync_wlast),
        .axiIn_bvalid   (cpu_sync_bvalid),
        .axiIn_bready   (cpu_sync_bready),
        .axiIn_bid      (cpu_sync_bid),
        .axiIn_bresp    (cpu_sync_bresp),
        .axiIn_arvalid  (cpu_sync_arvalid),
        .axiIn_arready  (cpu_sync_arready),
        .axiIn_araddr   (cpu_sync_araddr),
        .axiIn_arid     (cpu_sync_arid),
        .axiIn_arlen    (cpu_sync_arlen),
        .axiIn_arsize   (cpu_sync_arsize),
        .axiIn_arburst  (cpu_sync_arburst),
        .axiIn_arlock   (cpu_sync_arlock[0]),
        .axiIn_arcache  (cpu_sync_arcache),
        .axiIn_arprot   (cpu_sync_arprot),
        .axiIn_rvalid   (cpu_sync_rvalid),
        .axiIn_rready   (cpu_sync_rready),
        .axiIn_rdata    (cpu_sync_rdata),
        .axiIn_rid      (cpu_sync_rid),
        .axiIn_rresp    (cpu_sync_rresp),
        .axiIn_rlast    (cpu_sync_rlast),
        //slave 0 - ram
        .axiOut_0_awvalid   (ram_awvalid),
        .axiOut_0_awready   (ram_awready),
        .axiOut_0_awaddr    (ram_awaddr),
        .axiOut_0_awid      (ram_awid),
        .axiOut_0_awlen     (ram_awlen),
        .axiOut_0_awsize    (ram_awsize),
        .axiOut_0_awburst   (ram_awburst),
        .axiOut_0_awlock    (ram_awlock),
        .axiOut_0_awcache   (ram_awcache),
        .axiOut_0_awprot    (ram_awprot),
        .axiOut_0_wvalid    (ram_wvalid),
        .axiOut_0_wready    (ram_wready),
        .axiOut_0_wdata     (ram_wdata),
        .axiOut_0_wstrb     (ram_wstrb),
        .axiOut_0_wlast     (ram_wlast),
        .axiOut_0_bvalid    (ram_bvalid),
        .axiOut_0_bready    (ram_bready),
        .axiOut_0_bid       (ram_bid),
        .axiOut_0_bresp     (ram_bresp),
        .axiOut_0_arvalid   (ram_arvalid),
        .axiOut_0_arready   (ram_arready),
        .axiOut_0_araddr    (ram_araddr),
        .axiOut_0_arid      (ram_arid),
        .axiOut_0_arlen     (ram_arlen),
        .axiOut_0_arsize    (ram_arsize),
        .axiOut_0_arburst   (ram_arburst),
        .axiOut_0_arlock    (ram_arlock),
        .axiOut_0_arcache   (ram_arcache),
        .axiOut_0_arprot    (ram_arprot),
        .axiOut_0_rvalid    (ram_rvalid),
        .axiOut_0_rready    (ram_rready),
        .axiOut_0_rdata     (ram_rdata),
        .axiOut_0_rid       (ram_rid),
        .axiOut_0_rresp     (ram_rresp),
        .axiOut_0_rlast     (ram_rlast),
        //slave 1 - uart
        .axiOut_1_awvalid   (uart_awvalid),
        .axiOut_1_awready   (uart_awready),
        .axiOut_1_awaddr    (uart_awaddr),
        .axiOut_1_awid      (uart_awid),
        .axiOut_1_awlen     (uart_awlen),
        .axiOut_1_awsize    (uart_awsize),
        .axiOut_1_awburst   (uart_awburst),
        .axiOut_1_awlock    (uart_awlock[0]),
        .axiOut_1_awcache   (uart_awcache),
        .axiOut_1_awprot    (uart_awprot),
        .axiOut_1_wvalid    (uart_wvalid),
        .axiOut_1_wready    (uart_wready),
        .axiOut_1_wdata     (uart_wdata),
        .axiOut_1_wstrb     (uart_wstrb),
        .axiOut_1_wlast     (uart_wlast),
        .axiOut_1_bvalid    (uart_bvalid),
        .axiOut_1_bready    (uart_bready),
        .axiOut_1_bid       (uart_bid),
        .axiOut_1_bresp     (uart_bresp),
        .axiOut_1_arvalid   (uart_arvalid),
        .axiOut_1_arready   (uart_arready),
        .axiOut_1_araddr    (uart_araddr),
        .axiOut_1_arid      (uart_arid),
        .axiOut_1_arlen     (uart_arlen),
        .axiOut_1_arsize    (uart_arsize),
        .axiOut_1_arburst   (uart_arburst),
        .axiOut_1_arlock    (uart_arlock[0]),
        .axiOut_1_arcache   (uart_arcache),
        .axiOut_1_arprot    (uart_arprot),
        .axiOut_1_rvalid    (uart_rvalid),
        .axiOut_1_rready    (uart_rready),
        .axiOut_1_rdata     (uart_rdata),
        .axiOut_1_rid       (uart_rid),
        .axiOut_1_rresp     (uart_rresp),
        .axiOut_1_rlast     (uart_rlast),
        //slave 2 - sm
		`ifdef USE_CRYPTO
			.axiOut_2_awvalid   (sm_awvalid),
			.axiOut_2_awready   (sm_awready),
			.axiOut_2_awaddr    (sm_awaddr),
			.axiOut_2_awid      (sm_awid),
			.axiOut_2_awlen     (sm_awlen),
			.axiOut_2_awsize    (sm_awsize),
			.axiOut_2_awburst   (sm_awburst),
			.axiOut_2_awlock    (sm_awlock[0]),
			.axiOut_2_awcache   (sm_awcache),
			.axiOut_2_awprot    (sm_awprot),
			.axiOut_2_wvalid    (sm_wvalid),
			.axiOut_2_wready    (sm_wready),
			.axiOut_2_wdata     (sm_wdata),
			.axiOut_2_wstrb     (sm_wstrb),
			.axiOut_2_wlast     (sm_wlast),
			.axiOut_2_bvalid    (sm_bvalid),
			.axiOut_2_bready    (sm_bready),
			.axiOut_2_bid       (sm_bid),
			.axiOut_2_bresp     (sm_bresp),
			.axiOut_2_arvalid   (sm_arvalid),
			.axiOut_2_arready   (sm_arready),
			.axiOut_2_araddr    (sm_araddr),
			.axiOut_2_arid      (sm_arid),
			.axiOut_2_arlen     (sm_arlen),
			.axiOut_2_arsize    (sm_arsize),
			.axiOut_2_arburst   (sm_arburst),
			.axiOut_2_arlock    (sm_arlock[0]),
			.axiOut_2_arcache   (sm_arcache),
			.axiOut_2_arprot    (sm_arprot),
			.axiOut_2_rvalid    (sm_rvalid),
			.axiOut_2_rready    (sm_rready),
			.axiOut_2_rdata     (sm_rdata),
			.axiOut_2_rid       (sm_rid),
			.axiOut_2_rresp     (sm_rresp),
			.axiOut_2_rlast     (sm_rlast),
		`else 
			.axiOut_2_arready   (1'b1),
			.axiOut_2_rid       (5'b0),
			.axiOut_2_rdata     (32'b0),
			.axiOut_2_rresp     (2'b0),
			.axiOut_2_rlast     (1'b0),
			.axiOut_2_rvalid    (1'b0),
			.axiOut_2_awready   (1'b1),
			.axiOut_2_wready    (1'b1),
			.axiOut_2_bid       (5'b0),
			.axiOut_2_bresp     (2'b0),
			.axiOut_2_bvalid    (1'b0),
		`endif
        //slave 3 - confreg
        .axiOut_3_awvalid   (confreg_awvalid),
        .axiOut_3_awready   (confreg_awready),
        .axiOut_3_awaddr    (confreg_awaddr),
        .axiOut_3_awid      (confreg_awid),
        .axiOut_3_awlen     (confreg_awlen),
        .axiOut_3_awsize    (confreg_awsize),
        .axiOut_3_awburst   (confreg_awburst),
        .axiOut_3_awlock    (confreg_awlock),
        .axiOut_3_awcache   (confreg_awcache),
        .axiOut_3_awprot    (confreg_awprot),
        .axiOut_3_wvalid    (confreg_wvalid),
        .axiOut_3_wready    (confreg_wready),
        .axiOut_3_wdata     (confreg_wdata),
        .axiOut_3_wstrb     (confreg_wstrb),
        .axiOut_3_wlast     (confreg_wlast),
        .axiOut_3_bvalid    (confreg_bvalid),
        .axiOut_3_bready    (confreg_bready),
        .axiOut_3_bid       (confreg_bid),
        .axiOut_3_bresp     (confreg_bresp),
        .axiOut_3_arvalid   (confreg_arvalid),
        .axiOut_3_arready   (confreg_arready),
        .axiOut_3_araddr    (confreg_araddr),
        .axiOut_3_arid      (confreg_arid),
        .axiOut_3_arlen     (confreg_arlen),
        .axiOut_3_arsize    (confreg_arsize),
        .axiOut_3_arburst   (confreg_arburst),
        .axiOut_3_arlock    (confreg_arlock),
        .axiOut_3_arcache   (confreg_arcache),
        .axiOut_3_arprot    (confreg_arprot),
        .axiOut_3_rvalid    (confreg_rvalid),
        .axiOut_3_rready    (confreg_rready),
        .axiOut_3_rdata     (confreg_rdata),
        .axiOut_3_rid       (confreg_rid),
        .axiOut_3_rresp     (confreg_rresp),
        .axiOut_3_rlast     (confreg_rlast)
        );
	//AXI module ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
	
	
	//AXI SRAM module ----------------------------------------
    axi_wrap_ram_sp_ext u_axi_ram(
        .aclk           (sys_clk),
        .aresetn        (sys_resetn),
        //ar
        .axi_arid       (ram_arid),
        .axi_araddr     (ram_araddr),
        .axi_arlen      (ram_arlen),
        .axi_arsize     (ram_arsize),
        .axi_arburst    (ram_arburst),
        .axi_arlock     (ram_arlock),
        .axi_arcache    (ram_arcache),
        .axi_arprot     (ram_arprot),
        .axi_arvalid    (ram_arvalid),
        .axi_arready    (ram_arready),
        //r
        .axi_rid        (ram_rid),
        .axi_rdata      (ram_rdata), 
        .axi_rresp      (ram_rresp),
        .axi_rlast      (ram_rlast),
        .axi_rvalid     (ram_rvalid),
        .axi_rready     (ram_rready),
        //aw
        .axi_awid       (ram_awid),
        .axi_awaddr     (ram_awaddr),
        .axi_awlen      (ram_awlen),
        .axi_awsize     (ram_awsize),
        .axi_awburst    (ram_awburst),
        .axi_awlock     (ram_awlock),
        .axi_awcache    (ram_awcache),
        .axi_awprot     (ram_awprot),
        .axi_awvalid    (ram_awvalid),
        .axi_awready    (ram_awready),
        //w
        .axi_wdata      (ram_wdata),
        .axi_wstrb      (ram_wstrb),
        .axi_wlast      (ram_wlast),
        .axi_wvalid     (ram_wvalid),
        .axi_wready     (ram_wready),
        //b
        .axi_bid        (ram_bid),
        .axi_bresp      (ram_bresp),
        .axi_bvalid     (ram_bvalid),
        .axi_bready     (ram_bready),
		//addr
		.base_ram_addr 	( base_ram_addr_o      ),  
		.base_ram_be_n 	( base_ram_be_n_o      ),
		.base_ram_ce_n 	( base_ram_ce_n_o      ),  
		.base_ram_oe_n 	( base_ram_oe_n_o      ),  
		.base_ram_we_n 	( base_ram_we_n_o      ),  
		.ext_ram_addr  	( ext_ram_addr_o       ),  
		.ext_ram_be_n  	( ext_ram_be_n_o       ),  
		.ext_ram_ce_n  	( ext_ram_ce_n_o       ),  
		.ext_ram_oe_n  	( ext_ram_oe_n_o       ),  
		.ext_ram_we_n  	( ext_ram_we_n_o       ),  
		//data
		.base_ram_data_i    ( base_ram_data_i  ),  
		.base_ram_data_o    ( base_ram_data_o  ),  
		.base_ram_data_oe   ( base_ram_data_oe ),  
		.ext_ram_data_i     ( ext_ram_data_i   ),  
		.ext_ram_data_o     ( ext_ram_data_o   ),  
		.ext_ram_data_oe    ( ext_ram_data_oe  )  
        ); 
	//AXI SRAM module ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
	
	
	//AXI uart module ----------------------------------------
    axi_uart_controller u_axi_uart_controller(
        .clk            (sys_clk),
        .rst_n          (sys_resetn),
        //axi
        .axi_s_awid     (uart_awid),
        .axi_s_awaddr   (uart_awaddr),
        .axi_s_awlen    (uart_awlen),
        .axi_s_awsize   (uart_awsize),
        .axi_s_awburst  (uart_awburst),
        .axi_s_awlock   (uart_awlock),
        .axi_s_awcache  (uart_awcache),
        .axi_s_awprot   (uart_awprot),
        .axi_s_awvalid  (uart_awvalid),
        .axi_s_awready  (uart_awready),
        .axi_s_wid      (uart_awid),	//AXI3兼容模式
        .axi_s_wdata    (uart_wdata),
        .axi_s_wstrb    (uart_wstrb),
        .axi_s_wlast    (uart_wlast),
        .axi_s_wvalid   (uart_wvalid),
        .axi_s_wready   (uart_wready),
        .axi_s_bid      (uart_bid),
        .axi_s_bresp    (uart_bresp),
        .axi_s_bvalid   (uart_bvalid),
        .axi_s_bready   (uart_bready),
        .axi_s_arid     (uart_arid),
        .axi_s_araddr   (uart_araddr),
        .axi_s_arlen    (uart_arlen),
        .axi_s_arsize   (uart_arsize),
        .axi_s_arburst  (uart_arburst),
        .axi_s_arlock   (uart_arlock),
        .axi_s_arcache  (uart_arcache),
        .axi_s_arprot   (uart_arprot),
        .axi_s_arvalid  (uart_arvalid),
        .axi_s_arready  (uart_arready),
        .axi_s_rid      (uart_rid),
        .axi_s_rdata    (uart_rdata), 
        .axi_s_rresp    (uart_rresp),
        .axi_s_rlast    (uart_rlast),
        .axi_s_rvalid   (uart_rvalid),
        .axi_s_rready   (uart_rready),
        //dma
        .apb_rw_dma     (1'b0),
        .apb_psel_dma   (1'b0),
        .apb_enab_dma   (1'b0),
        .apb_addr_dma   (20'b0),
        .apb_valid_dma  (1'b0),
        .apb_wdata_dma  (32'b0),
        .apb_rdata_dma  (),
        .apb_ready_dma  (),
        .dma_grant      (),
        .dma_req_o      (),
        .dma_ack_i      (1'b0),
		//for chip io
        .uart0_txd_i    (UART_TX_i),
        .uart0_txd_o    (UART_TX_o),
        .uart0_txd_oe   (UART_TX_oe),
        .uart0_rxd_i    (UART_RX_i),
        .uart0_rxd_o    (UART_RX_o),
        .uart0_rxd_oe   (UART_RX_oe),
		//for chip io - not connetc
        .uart0_rts_o    (uart0_rts_o),
        .uart0_dtr_o    (uart0_dtr_o),
        .uart0_cts_i    (uart0_cts_i),
        .uart0_dsr_i    (uart0_dsr_i),
        .uart0_dcd_i    (uart0_dcd_i),
        .uart0_ri_i     (uart0_ri_i),
        .uart0_int      (uart0_int)
        );
	//AXI uart module ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
	
	
	//AXI confreg module -------------------------------------
    confreg #(.SIMULATION(SIMULATION)) u_confreg(
        .aclk           (sys_clk),
        .aresetn        (sys_resetn),
        .cpu_clk        (cpu_clk),
        .cpu_resetn     (cpu_resetn),
		//axi
        .s_awid         (confreg_awid),
        .s_awaddr       (confreg_awaddr),
        .s_awlen        (confreg_awlen),
        .s_awsize       (confreg_awsize),
        .s_awburst      (confreg_awburst),
        .s_awlock       (confreg_awlock),
        .s_awcache      (confreg_awcache),
        .s_awprot       (confreg_awprot),
        .s_awvalid      (confreg_awvalid),
        .s_wid          (confreg_awid),		//AXI3兼容模式
        .s_wdata        (confreg_wdata),
        .s_wstrb        (confreg_wstrb),
        .s_wlast        (confreg_wlast),
        .s_wvalid       (confreg_wvalid),
        .s_bready       (confreg_bready),
        .s_arid         (confreg_arid),
        .s_araddr       (confreg_araddr),
        .s_arlen        (confreg_arlen),
        .s_arsize       (confreg_arsize),
        .s_arburst      (confreg_arburst),
        .s_arlock       (confreg_arlock),
        .s_arcache      (confreg_arcache),
        .s_arprot       (confreg_arprot),
        .s_arvalid      (confreg_arvalid),
        .s_rready       (confreg_rready),
        .s_awready      (confreg_awready),
        .s_wready       (confreg_wready),
        .s_bid          (confreg_bid),
        .s_bresp        (confreg_bresp),
        .s_bvalid       (confreg_bvalid),
        .s_arready      (confreg_arready),
        .s_rid          (confreg_rid),
        .s_rdata        (confreg_rdata),
        .s_rresp        (confreg_rresp),
        .s_rlast        (confreg_rlast),
        .s_rvalid       (confreg_rvalid),
        //for chip io
        .switch         (dip_sw_i),
        .touch_btn      (touch_btn_i),
        .led            (leds_o),
        .dpy0           (dpy0_o),
        .dpy1           (dpy1_o),
		//for int sys
        .confreg_int    (confreg_int),
		.int_exti		(confreg_exti)
        );
	//AXI confreg module ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
	
	
	//AXI SM module ----------------------------------------
	`ifdef USE_CRYPTO
		axi_crypto #(.SIMULATION(SIMULATION)) u_axi_crypto (
			.aclk           (sys_clk),
			.aresetn        (sys_resetn),
			.sm2_clk        (sm2_clk),
			.sm2_resetn     (sm2_resetn),
			//axi
			.s_awid         (sm_awid),
			.s_awaddr       (sm_awaddr),
			.s_awlen        (sm_awlen),
			.s_awsize       (sm_awsize),
			.s_awburst      (sm_awburst),
			.s_awlock       (sm_awlock[0]),
			.s_awcache      (sm_awcache),
			.s_awprot       (sm_awprot),
			.s_awvalid      (sm_awvalid),
			.s_wid          (sm_awid),		//AXI3兼容模式
			.s_wdata        (sm_wdata),
			.s_wstrb        (sm_wstrb),
			.s_wlast        (sm_wlast),
			.s_wvalid       (sm_wvalid),
			.s_bready       (sm_bready),
			.s_arid         (sm_arid),
			.s_araddr       (sm_araddr),
			.s_arlen        (sm_arlen),
			.s_arsize       (sm_arsize),
			.s_arburst      (sm_arburst),
			.s_arlock       (sm_arlock[0]),
			.s_arcache      (sm_arcache),
			.s_arprot       (sm_arprot),
			.s_arvalid      (sm_arvalid),
			.s_rready       (sm_rready),
			.s_awready      (sm_awready),
			.s_wready       (sm_wready),
			.s_bid          (sm_bid),
			.s_bresp        (sm_bresp),
			.s_bvalid       (sm_bvalid),
			.s_arready      (sm_arready),
			.s_rid          (sm_rid),
			.s_rdata        (sm_rdata),
			.s_rresp        (sm_rresp),
			.s_rlast        (sm_rlast),
			.s_rvalid       (sm_rvalid),
			
			.sm2_done_int	(sm2_done_int),
			.sm3_done_int	(sm3_done_int),
			.sm4_done_int	(sm4_done_int)
			);
	`endif
	//AXI SM module ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
	
endmodule

